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INTEGRATED CIRCUITS
DATA SHEET
UDA1335H Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
Preliminary specification File under Integrated Circuits, IC01 1998 Aug 28
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
UDA1335H
FEATURES General * USB stereo audio record and playback system with 20 bits analog-to-digital conversion (with 5 to 55 kHz sample frequency range) and adaptive 20 bits digital-to-analog conversion (with 5 to 55 kHz sample frequency range) with integrated filtering * USB-compliant audio/HID device * Supports 12 Mbits/s `full speed' serial data transmission * Fully automatic `Plug-and-Play' operation * Supports multiple audio data formats (8, 16 and 24 bits) * 5.0 and 3.3 V power supply * Low power consumption * Efficient power management * On-chip master clock oscillators, only an external crystal is required * High linearity * Wide dynamic range * Superior signal-to-noise ratio * Low total harmonic distortion * Supports headphone and line output * Partly programmable USB descriptors and configuration via the I2C-bus. Sound processing (for digital-to analog conversion) * Separate digital volume control for left and right channel * Soft mute * Digital bass and treble tone control * External Digital Sound Processor (DSP) option possible via standard I2S-bus or Japanese digital I/O format * Selectable clipping prevention * Selectable Dynamic Bass Boost (DBB) * On-chip digital de-emphasis.
Document references * "USB Specification" * "USB Device Class Definition for Audio Devices" * "Device Class Definition for Human Interface Devices (HID)" * "USB HID Usage Table" * "USB Common Class Specification". GENERAL DESCRIPTION The UDA1335H is a stereo CMOS codec incorporating bitstream converters designed for implementation in USB-compliant audio peripherals and multimedia audio applications. The UDA1335H is an adaptive asynchronous sink USB audio device with a continuous sampling frequency range from 5 to 55 kHz. It contains a USB interface, an embedded microcontroller, an Analog-to-Digital Interface (ADIF) and an Asynchronous Digital-to-Analog Converter (ADAC). The USB interface is the interface between the USB, the ADIF, the ADAC and the microcontroller. The USB interface consists of an analog front-end and a USB processor. The analog front-end transforms the differential USB data into a digital data stream. The USB processor buffers the incoming and outgoing data from the analog front-end and handles all low-level USB protocols. The USB processor selects the relevant data from the universal serial bus, performs an extensive error detection and separates control information (input and output) and audio information (input and output). The control information is made accessible to the microcontroller. The audio information received from the PC becomes available at the digital I/O output or is fed directly to the ADAC. The audio information to be transmitted to the PC is delivered by the ADIF or by the digital I2S-bus interface. The microcontroller handles the high-level USB protocols, translates the incoming control requests and manages the user interface via general purpose pins and an I2C-bus.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
The firmware for the microcontroller must be located in an external (E)PROM. The ADAC enables the wide and continuous range of input sampling frequencies. By means of a Sample Frequency Generator (SFG), the ADAC is able to reconstruct the average sample frequency from the incoming audio samples. The ADAC also performs the sound processing. The ADAC consists of a FIFO, a unique audio feature processing DSP, the SFG, digital upsampling filters, a variable hold register, a Noise Shaper (NS) and a Filter Stream DAC (FSDAC) with integrated filter and line output drivers. The audio information is applied to the ADAC via the USB processor or via the digital I/O input. The ADIF consists of an Programmable Gain Amplifier (PGA), an Analog-to-Digital Converter (ADC) and a Decimator Filter (DF). An Analog Phase Lock Loop (APLL) or oscillator is used for clocking the ADIF. The clock frequency for the ADIF can be controlled via the microcontroller. Several clock frequencies are possible for sampling the analog input signal at different sampling rates. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UDA1335H QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
UDA1335H
Via the digital I/O-bus, an external DSP can be used for adding extra sound processing features for the audio received from the PC. The UDA1335H supports the digital I/O and the I2S-bus interface, with standard I2S-bus data input format and the LSB justified serial data input format with word lengths of 16, 18 and 20 bits. The wide dynamic range of the bitstream conversion technique used in the UDA1335H guarantees a high audio sound quality. APPLICATIONS * USB monitors * USB speakers * USB headsets * USB telephone/answering machines * USB links in consumer audio devices.
VERSION SOT319-2
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
QUICK REFERENCE DATA SYMBOL Supplies VDDE VDDI IDD(tot) IDD(tot)(ps) supply voltage periphery supply voltage core total supply current total supply current in power-saving note 1 mode 4.75 3.0 - - 5.0 3.3 60 360 PARAMETER CONDITIONS MIN. TYP.
UDA1335H
MAX.
UNIT
5.25 3.6 tbf -
V V mA A
Dynamic performance DAC (THD + N)/S total harmonic distortion plus noise-to-signal ratio fs = 44.1 kHz; RL = 5 k fi = 1 kHz (0 dB) fi = 1 kHz (-60 dB) S/N Vo(FS)(rms) signal-to-noise ratio at bipolar zero full-scale output voltage (RMS value) - - - - A-weighted at code 0000H 90 VDD = 3.3 V - -90 0.0032 -30 3.2 95 0.66 -80 0.01 -20 10 - - dB % dB % dBA V
Dynamic performance PGA and ADC (THD + N)/S total harmonic distortion plus noise-to-signal ratio fs = 44.1 kHz; PGA gain = 0 dB fi = 1 kHz; (0 dB); Vi = 1.0 V (RMS) fi = 1 kHz (-60 dB) S/N signal-to-noise ratio Vi = 0.0 V - - - - 90 General characteristics fi(s) Tamb Note 1. Exclusive the IDDE current which depends on the components connected to the I/O pins. audio input sample frequency operating ambient temperature 5 0 - 25 55 70 kHz C -85 0.0056 -30 3.2 95 -80 0.01 -20 10.0 - dB % dB % dBA
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
BLOCK DIAGRAM
UDA1335H
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CLK 27 VSSX XTAL1b XTAL2b VDDX VDDA3 XTAL2a XTAL1a VSSA3 24 25 26 28 52 53 54 55 OSC ADC ANALOG PLL USB-PROCESSOR OSC 48 MHz TIMING ANALOG FRONT-END D+ 8 D- 6 P0.7 to P0.0 7, 5, 3, 64, 62, 60, 58, 56 P2.0 to P2.7 14, 16, 18, 20, 22, 23, 29, 30 9 10 11 12 32 33 38 39 42 44 VDDI VSSI VSSE VDDE VDDO VSSO VDDA1 VSSA1 VDDA2 VSSA2
GP2/DO GP3/WSO GP4/BCKO GP1/DI GP0/BCKI GP5/WSI
63 1 2 13 17 15 DIGITAL I/O 19 MICROCONTROLLER 21 SCL SDA
PSEN
31
MUX
FIFO
DA WS BCK
57 59 61 I2S-BUS INTERFACE DECIMATOR FILTER
SAMPLE FREQUENCY GENERATOR
AUDIO FEATURE PROCESSING DSP
UPSAMPLE FILTERS TEST CONTROL BLOCK VARIABLE HOLD REGISTER
4 35 36
SHTCB TC RTCB
EA ALE
48 50
VINL
43
PGA
LEFT ADC
3rd-ORDER NOISE SHAPER
UDA1335H
VINR 47 PGA RIGHT ADC
LEFT DAC
- + +
34
VOUTL
37
VOUTR
REFERENCE VOLTAGE VRN VRP 49 51
RIGHT DAC
-
45, 46 n.c.
41 Vref(AD)
40 Vref(DA)
MBK838
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
PINNING SYMBOL GP3/WSO GP4/BCKO P0.5 SHTCB P0.6 D- P0.7 D+ VDDI VSSI VSSE VDDE GP1/DI P2.0 GP5/WSI P2.1 GP0/BCKI P2.2 SCL P2.3 SDA P2.4 P2.5 VSSX XTAL1b XTAL2b CLK VDDX P2.6 P2.7 PSEN VDDO VSSO VOUTL TC RTCB VOUTR VDDA1 VSSA1 1998 Aug 28 PIN QFP64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 I/O I/O I/O I/O I I/O I/O I/O I/O - - - - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - I O O - I/O I/O I/O - - O I I O - - DESCRIPTION general purpose pin 3 or word select output general purpose pin 4 or bit clock output port 0.5 of the microcontroller shift clock of the test control block (active HIGH) port 0.6 of the microcontroller
UDA1335H
negative data line of the differential data bus, conforms to the USB standard port 0.7 of the microcontroller positive data line of the differential data bus, conforms to the USB standard digital supply voltage for core digital ground for core digital ground for I/O pads digital supply voltage for I/O pads general purpose pin 1 or data input port 2.0 of the microcontroller general purpose pin 5 or word select input port 2.1 of the microcontroller general purpose pin 0 or bit clock input port 2.2 of the microcontroller serial clock line I2C-bus port 2.3 of the microcontroller serial data line I2C-bus port 2.4 of the microcontroller port 2.5 of the microcontroller crystal oscillator ground (48 MHz) crystal input (analog; 48 MHz) crystal output (analog; 48 MHz) 48 MHz clock output signal supply crystal oscillator (48 MHz) port 2.6 of the microcontroller port 2.7 of the microcontroller program store enable (active LOW) supply voltage for operational amplifier operational amplifier ground voltage output left channel test control input (active HIGH) asynchronous reset input of the test control block (active HIGH) voltage output right channel analog supply voltage 1 analog ground 1 6
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
SYMBOL Vref(DA) Vref(AD) VDDA2 VINL VSSA2 n.c. n.c. VINR EA VRN ALE VRP VDDA3 XTAL2a XTAL1a VSSA3 P0.0 DA P0.1 WS P0.2 BCK P0.3 GP2/DO P0.4 PIN QFP64 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 I/O O O - I - - - I - I - I - O I - I/O I I/O I I/O I I/O I/O I/O reference voltage output DAC reference voltage output ADC analog supply voltage 2 input signal left channel PGA analog ground 2 not connected not connected input signal right channel PGA external access (active LOW) negative reference input voltage ADC address latch enable (active HIGH) positive reference input voltage ADC supply voltage for crystal oscillator and analog PLL crystal output (analog; ADC) crystal input (analog; ADC) crystal oscillator and analog PLL ground port 0.0 of the microcontroller data Input (digital) port 0.1 of the microcontroller word select input (digital) port 0.2 of the microcontroller bit clock input (digital) port 0.3 of the microcontroller general purpose pin 2 or data output port 0.4 of the microcontroller DESCRIPTION
UDA1335H
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
UDA1335H
63 GP2/DO
54 XTAL1a
53 XTAL2a
GP3/WSO 1 GP4/BCKO 2 P0.5 3 SHTCB 4 P0.6 5 D- 6 P0.7 7 D+ 8 VDDI 9 VSSI 10 VSSE 11 VDDE 12 GP1/DI 13 P2.0 14 GP5/WSI 15 P2.1 16 GP0/BCKI 17 P2.2 18 SCL 19 P2.3 20 SDA 21 P2.4 22 P2.5 23 VSSX 24 XTAL1b 25 XTAL2b 26 CLK 27 VDDX 28 P2.6 29 P2.7 30 PSEN 31 VDDO 32
55 VSSA3
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52 VDDA3 51 VRP 50 ALE 49 VRN 48 EA 47 VINR 46 n.c. 45 n.c. 44 VSSA2 43 VINL 42 VDDA2 41 Vref(AD) 40 Vref(DA) 39 VSSA1 38 VDDA1 37 VOUTR 36 RTCB 35 TC 34 VOUTL 33 VSSO
MBK841
64 P0.4
62 P0.3
60 P0.2
58 P0.1
UDA1335H
Fig.2 Pin configuration.
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56 P0.0
61 BCK
59 WS
57 DA
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
FUNCTIONAL DESCRIPTION The Universal Serial Bus (USB) Data and power is transferred via the USB over a 4-wire cable. The signalling occurs over two wires and point-to-point segments. The signals on each segment are differentially driven into a cable of 90 intrinsic impedance. The differential receiver features input sensitivity of at least 200 mV and sufficient common mode rejection. The analog front-end The analog front-end is an on-chip generic USB transceiver. It is designed to allow voltage levels up to VDD from standard or programmable logic to interface with the physical layer of the USB. It is capable of receiving and transmitting serial data at full speed (12 Mbits/s). The USB processor The USB processor forms the interface between the analog front-end, the ADIF, the ADAC and the microcontroller. The USB processor consists of: * The Philips Serial Interface Engine (PSIE) * The Memory Management Unit (MMU) * The Audio Sample Redistribution (ASR) module. The Philips Serial Interface Engine and Memory Management Unit (PSIE/MMU) The PSIE/MMU translates the electrical USB signals into bytes and signals. Depending upon the USB device address and the USB endpoint address, the USB data is directed to the correct endpoint buffer on the PSIE/MMU interface. The data transfer could be of bulk, isochronous, control or interrupt type. The USB device address is configured during the enumeration process. The UDA1335H has four endpoints. These are: * Control endpoint 0 * Status interrupt endpoint * Isochronous data sink endpoint * Isochronous data source endpoint. The amount of bytes/packet on the control endpoint is limited by the PSIE/MMU hardware to 8 bytes/packet. The PSIE is the digital front-end of the USB processor. This module recovers the 12 MHz USB clock, detects the USB sync word and handles all low-level USB protocols and error checking.
UDA1335H
The MMU is the digital back-end of the USB processor. It handles the temporary data storage of all USB packets that are received or sent over the bus. Three types of packets are defined on the USB. These are: * Token packets * Data packets * Handshake packets. The token packet contains information about the destination of the data packet. The audio data is transferred via an isochronous data sink endpoint or source endpoint and, consequently, no handshaking mechanism is used. The MMU also generates a 1 kHz clock that is locked to the USB Start Of Frame (SOF) token. The Audio Sample Redistribution (ASR) The ASR reads the audio samples from the MMU and distributes these samples equidistant over a 1 ms frame period. The distributed audio samples are translated by the digital I/O module to standard I2S-bus format or Japanese digital I/O format. The ASR generates the bit clock and the word select signal of the digital I/O. The digital I/O formats the received audio samples to one of the four specified serial digital audio formats (I2S-bus, 16, 18 or 20 bits LSB-justified). The microcontroller The microcontroller receives the control information selected from the USB by the USB processor. It handles the high-level USB protocols and the user interfaces. The major task of the software process, that is mapped upon the microcontroller, is to control the different modules of the UDA1335H in such a way that it behaves as a USB device. Therefore the microcontroller: * Interprets the USB requests and maps them upon the UDA1335H application * Controls the internal operation of the UDA1335H, the digital I/O pins and the GP I/O pins * Communicates with the external world (external controller, EEPROM) using the I2C-bus facility and the GP I/O pins. The microcontroller does not handle the audio stream. The UDA1335H will be delivered with USB compliant firmware. The firmware must be located in an external (E)PROM.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
The Analog-to-Digital Interface (ADIF) The ADIF is used for sampling an analog input signal from a microphone or line input and sending the audio samples to the USB interface. The ADIF consists of a stereo Programmable Gain Amplifier (PGA), a stereo Analog-to-Digital Converter (ADC) and Decimation Filters (DFs). The sample frequency of the ADC is determined by the ADC clock (see Section "The timing of the analog-to-digital interface"). The user can also select a digital serial input instead of an analog input. In this event the sample frequency is determined by the continuous WS clock with a range between 5 to 55 kHz. Digital serial input is possible with four formats (I2S-bus, 16, 18 or 20 bits LSB-justified). The Programmable Gain Amplifier circuit (PGA) This circuit can be used for a microphone or line input. The input audio signals can be amplified by 7 different gains. The preferred gain is selected during start-up of the device (configuration map). The gain settings are given in Table 1. Table 1 The selectable gains of the PGA GAIN -3 0 3 9 15 21 27 UNIT dB dB dB dB dB dB dB 00 01 10 11 The Decimation Filter (DF)
UDA1335H
The decimator filter converts the audio data from 128fs down to 1fs with a word width of 8, 16 or 24 bits. This data will be transmitted over the USB as mono or stereo in 1, 2 or 3 bytes/sample. The decimator filters are clocked by the ADC clock. The timing of the analog-to-digital interface The clock source of the ADIF is the analog PLL or the ADC oscillator. The preferred clock source can be selected during start-up of the device (configuration map). The ADC clock used for the ADC and decimation filters is obtained by dividing the clock signal coming from the analog PLL or from the ADC oscillator by a factor Q. Using the analog PLL the user can select 3 clock frequencies via the microcontroller. By connecting the appropriate crystal the user can choose any clock signal between 8.192 and 14.08 MHz via the ADC oscillator. Table 2 The analog PLL clock output frequencies APLL CLOCK FREQUENCY (MHz) 11.2896 8.1920 12.2880 11.2896
FCODE
SETTING 000 001 010 011 100 101 11X
The dividing factor Q can be selected via the microcontroller. With this dividing factor Q the user can select a range of ADC clock signals allowing several different sample frequencies (see Table 3).
The Analog-to-Digital Converter (ADC) The stereo ADC of the UDA1335H consists of two 3rd-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The oversampling ratio is 128. Both ADCs can be switched off in power saving mode (left and right separate). The ADC clock is generated by the analog PLL or the ADC oscillator.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
Table 3
UDA1335H
ADC clock frequencies and sample frequencies based upon using the APLL as a clock source (analog input topology 1), see note 1. DIVIDE FACTOR Q 1 2 4 8 1 2 4 8 1 2 4 8 ADC CLOCK FREQUENCY (MHz) 4.096 2.048 1.024 0.512 (not supported) 5.6448 2.8224 1.4112 0.7056 6.144 3.072 1.536 0.768 SAMPLE FREQUENCY (kHz) 32 16 8 4 (not supported) 44.1 22.05 11.025 5.5125 48 24 12 6
APLL CLOCK FREQUENCY (MHz) 8.1920
11.2896
12.2880
Note 1. By using the APLL as a clock source 12 sample frequencies will be reported to the USB host. Table 4 ADC clock frequencies and sample frequencies based upon using the OSCAD as a clock source (analog input topology 4), see note 1 DIVIDE FACTOR Q Q(3) ADC CLOCK FREQUENCY (MHz) fosc/(2Q) SAMPLE FREQUENCY (kHz) fosc/(256Q)(4)
OSCAD CLOCK FREQUENCY (MHz) fosc(2) Notes
1. By using the OSCAD as a clock source, the sample frequency and the Q dividing factor must be filled in the configuration map. Only this one sample frequency will be reported to the USB host. 2. The oscillator frequency (and therefore the crystal) of OSCAD must be between 8.192 and 14.08 MHz. 3. The Q factor can be 1, 2, 4 or 8. 4. Sample frequencies below 5 kHz and above 55 kHz are not supported.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
The Asynchronous Digital-to-Analog Converter (ADAC) The ADAC receives USB audio information from the USB processor or from the digital I/O-bus. The ADAC is able to reconstruct the sample clock from the rate at which the audio samples arrive and handles the audio sound processing. After the processing, the audio signal is upsampled, noise-shaped and converted to analog output voltages capable of driving a line output. The ADAC consists of: * A Sample Frequency Generator (SFG) * FIFO registers * An audio feature processing DSP * Two digital upsampling filters and a variable hold register * A digital Noise Shaper (NS) * A Filter Stream DAC (FSDAC) with integrated filter and line output drivers. The Sample Frequency Generator (SFG) The SFG controls the timing signals for the asynchronous digital-to-analog conversion. By means of a digital PLL, the SFG automatically recovers the applied sampling frequency and generates the accurate timing signals for the audio feature processing DSP and the upsampling filters. First-In First-Out (FIFO) registers The FIFO registers are used to store the audio samples temporarily coming from the USB processor or from the digital I/O input. The use of a FIFO (in conjunction with the SFG) is necessary to remove all jitter present on the incoming audio signal. The audio feature processing DSP A DSP processes the sound features. The control and mapping of the sound features is explained in Section "Controlling the USB APRP". Depending on the sampling rate (fs) the DSP knows four frequency domains in which the treble and bass are regulated. The domain is chosen automatically. Table 5
UDA1335H
Frequency domains for audio processing by the DSP SAMPLE FREQUENCY (kHz) 5 to 12 12 to 25 25 to 40 40 to 55
DOMAIN 1 2 3 4
The upsampling filters and variable hold function After the audio feature processing DSP two upsampling filters and a variable hold function increase the oversampling rate to 128fs. The noise shaper A 3rd-order noise shaper converts the oversampled data to a noise-shaped bitstream for the FSDAC. The in-band quantization noise is shifted to frequencies well above the audio band. The Filter Stream DAC (FSDAC) The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed because of the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. USB Audio Playback Recording Peripheral (APRP) descriptors In a typical USB environment the PC has to know which kind of devices are connected. For this purpose each device contains a number of USB descriptors. These descriptors describe, from different points of view (USB configuration, USB interface and USB endpoint), the capabilities of a device. Each of them can be requested by the host. The collection of descriptors is denoted as a descriptor map. This descriptor map will be reported to the USB host during enumeration and on request. The USB descriptors and their most important fields, in relationship to the characteristics of the UDA1335H are explained briefly below.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
AUDIO FUNCTION TOPOLOGIES
UDA1335H
Four audio function Input topologies and two audio function output topologies are supported by the UDA1335H. Each configuration map can select only one Input and one output topology. The descriptors and the supported requests depend on the selected topologies in the active configuration map. Figures 3 and 4 illustrate the different audio Input and output topologies.
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INPUT TERMINAL
FEATURE UNIT
FU
OUTPUT TERMINAL
IT
OT
MBK530
Fig.3 One audio output function topology (with or without bass boost) is supported.
handbook, full pagewidth
Analog Input Terminal
IT
OT
Output Terminal
a. Analog topology 1 (using APLL clock source).
Input Terminal 1
IT
SELECTOR UNIT SU
OT
Output Terminal
Input Terminal 2
IT
b. Analog topology 2.
Digital Input Terminal
IT
OT
Output Terminal
c. Digital topology 3.
Analog Input Terminal
IT
OT
Output Terminal
MGL437
d. Analog topology 4 (using OSCAD clock source). Fig.4 Four input function topologies are supported.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
GENERAL DESCRIPTORS The UDA1335H supports one configuration containing a control interface, two audio interfaces and a HID interface. The descriptor map that describes this configuration is partly fixed and partly programmable. The programmable part can be retrieved from one of four configuration maps located in the firmware or from an I2C-bus EEPROM. At start-up time one of four internal configuration maps can be selected depending on the logical combination of GP3 and GP4. It is possible to overwrite this configuration map with a configuration map loaded from an I2C-bus EEPROM. AUDIO DEVICE CLASS SPECIFIC DESCRIPTORS The audio device class is partly specified with standard descriptors and partly with specific audio device class descriptors. The standard descriptors specify the number and the type of the interface or endpoint. The UDA1335H supports 7 different audio modes: * 8-bit PCM mono or stereo audio data * 16-bit PCM mono or stereo audio data * 24-bit PCM mono or stereo audio data * Zero bandwidth mode. Each mode is defined as an alternate setting of the audio interface, selectable with the standard audio streaming interface descriptor bAlternateSetting field. The seven alternate settings are described in more detail by the specific audio device class descriptors. The UDA1335H supports the input terminal, output terminal and the feature unit descriptors. The input and output terminals are not controllable via the USB. The feature unit provides the basic manipulation of the incoming logical channels. The supported sound features are: * Volume control * Mute control * Treble control * Bass control * Bass Boost control. The maximum number of audio data samples within a USB packet arriving on the isochronous sink endpoint is restricted by the buffer capacity of this isochronous endpoint. The maximum buffer capacity is 336 bytes/ms. The input terminals can be defined by means of wTerminalType. 1998 Aug 28 14
UDA1335H
THE STANDARD AUDIO STREAMING INTERFACE DESCRIPTOR
FOR THE ISOCHRONOUS DATA SINK ENDPOINT
In this section the descriptors are given for interface 1 which is used for receiving isochronous audio data from the host. Although in this specific UDA1335H application no endpoint control properties can be used on the isochronous adaptive sink endpoint, the descriptors are still necessary to inform the host about the definition of this endpoint: isochronous, adaptive, sink, continuous sampling frequency (at input side of this endpoint) with a lower boundary of 5 kHz and an upper boundary of 55 kHz. The audio class specific descriptors can be requested with the `Get Descriptor: configuration request', which returns all the descriptors, except the device descriptor. For each alternate setting with audio, a maximum bandwidth is claimed as indicated in the standard isochronous audio data endpoint descriptor wMaxPacketSize field. To allow a small overshoot in the number of audio samples per packet, the top sample frequency of 55 kHz is taken in the calculation of the bandwidth for each alternate setting. For each alternate setting, with its own isochronous audio data endpoint descriptor, wMaxPacketSize field is then defined as described in Table 6. Table 6 Audio bandwidth at each audio mode AUDIO MODE 8-bit PCM, mono 8-bit PCM, stereo 16-bit PCM, mono 16-bit PCM, stereo 24-bit PCM, mono 24-bit PCM, stereo wMaxPacketSize (HEX) 3800 7000 7000 E000 A800 5001
ALTERNATE SETTING 1 2 3 4 5 6
THE STANDARD AUDIO STREAMING INTERFACE DESCRIPTOR
FOR THE ISOCHRONOUS DATA SOURCE ENDPOINT
Interface 2 is used for sending isochronous audio data to the host. It has the same alternate settings as interface 1.
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
HUMAN INTERFACE DEVICE SPECIFIC DESCRIPTORS The inputs defined on the UDA1335H are transmitted via the USB to the host according to the HID class. The host responds with the appropriate settings via the audio device class for the audio related parts or via the HID class for the HID related inputs and outputs of the UDA1335H. A HID descriptor is necessary to inform the host about the conception of the user interface. The host communicates via the HID device driver using either the control pipe or the interrupt pipe. The UDA1335H is using USB endpoint 0 (control pipe) to respond to the HID specific `Get/Set Report request' to receive or transmit data from or to the UDA1335H. The UDA1335H uses the status interrupt endpoint as interrupt pipe for polling asynchronous data. The UDA1335H is a high-speed device. The maximum transaction size is 64 bytes per USB frame and the polling rate is defined at a maximum of every 1 ms. The host requests the configuration descriptor which includes the standard interface descriptor, the HID endpoint descriptor and the HID descriptor. The HID device driver of the host then requests the report descriptor. Report descriptors are composed of pieces of information about the device. Each piece of information is called an item. All items have a 1-byte prefix that contains the item tag, type and size. In the UDA1335H only the short item basic type is used. The hosts HID device driver will parse the report descriptor and the defined items. By examining all of these items, the HID class driver is able to determine the size and composition of data reports from the device. The main items of the UDA1335H are input reports. Input reports are sent via the interrupt pipe (UDA1335H USB endpoint 3). Input reports can be requested by the host via the control endpoint (USB endpoint 0). The UDA1335H supports a maximum of two push-buttons (six with I2C-bus expanders), which represent a certain feature of the UDA1335H. If pressed by the user the pushbutton will go to its `ON' state, if not pressed the push-button will go back to its `OFF' state. For more information about the input functions of the UDA1335H see the application documentation of the device. Controlling the USB APRP
UDA1335H
The sound features as defined in the "USB Device Class Definition for Audio Devices" are mapped on the UDA1335H specific feature registers by the microcontroller. These specific sound features are: * Volume control (separate for left and right stereo channels, no master channel) * Mute control (only master channel) * Treble control (only master channel) * Bass control (only master channel) * Dynamic bass boost control (only master channel). These specific features can be activated via the host (audio device class requests) or via the GP I/O pins (HID plus audio device class requests). The user is able to download the necessary configuration data for different applications (definition of the function of the GP pins, with or without digital I/O functionality etc.) via the configuration map. The mapping and control of the standard USB audio features and UDA1335H specific features is described below. Volume control Volume control is possible via the host or via predefined GP I/O pins. The setting of 0 dB is always referenced to the maximum available volume setting. Table 7 gives the mapping of wVolume value (as defined in the "USB Device Class Definition for Audio Devices") upon the actual volume setting of the USB APRP. When using the UDA1335H, the range is 0 dB down to -60 dB (in steps of 1 dB) and - dB. Independant control of `left'/'right' volume is possible. It should be noted that wVolumeLSB B7 to B0 are not used. Values above 0 dB are returned as 0 dB. The volume value at start-up of the device is defined in the selected configuration map. Balance control is possible via the separate volume control option of both channels. Therefore the characteristics of the balance control are equal to the volume control characteristics.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
Table 7 Volume control characteristics wVOLUME (MSB) B15 0 1 1 1 1 1 1 1 1 1 1 ... 1 1 1 1 ... 1 B14 0 1 1 1 1 1 1 1 1 1 1 ... 1 1 1 1 ... 0 B13 0 1 1 1 1 1 1 1 1 1 1 ... 0 0 0 0 ... 0 B12 0 1 1 1 1 1 1 1 1 1 1 ... 0 0 0 0 ... 0 B11 0 1 1 1 1 1 1 1 1 0 0 ... 0 0 0 0 ... 0 B10 0 1 1 1 1 0 0 0 0 1 1 ... 1 1 0 0 ... 0 B9 0 1 1 0 0 1 1 0 0 1 1 ... 0 0 1 1 ... 0 B8 0 1 0 1 0 1 0 1 0 1 0 ... 1 0 1 0 ... 0 VOLUME USB SIDE (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 ... -59 -60 -61 -62 ... -
UDA1335H
VOLUME USB APRP (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 ... -59 -60 - - ... -
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
Mute control Mute is one of the sound features as defined in the "USB Device Class Definition for Audio Devices". The mute control request data bMute controls the position of the mute switch. The position can be either on or off. When bMute is true the feature unit is muted. When bMute is false the feature unit is not muted. When the mute is active for the master channel, the value of the sample is decreased smoothly to zero following a raised cosine curve. There are 32 coefficients used to step down the value of the data, each one being used 32 times before stepping to the next. This amounts to a mute transition of 23 ms at fs = 44.1 kHz. When the mute is released, the samples are returned to the full level again following a raised cosine curve with the same coefficients being used in reversed order. Table 8 Treble control characteristics bTREBLE B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 TREBLE USB HOST (dB) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 ... 5.25 ... 7.25 ... 9.25 ... 31.75
UDA1335H
The mute, on the master channel is synchronized to the sample clock, so that operation always takes place on complete samples. A mute can be given via the host or by pressing a predefined GP pin. Treble control The treble control is available for the master channel of the UDA1335H. The treble range is from 0 to 6 dB in steps of 2 dB. It should be noted that the negative treble values as defined in the "USB Device Class Definition for Audio Devices" are not supported by the UDA1335H; values below 0 dB are returned as 0 dB. The corner frequency is 1500 Hz. Table 8 gives the mapping of the bTreble value upon the actual treble setting of the USB APRP.
TREBLE USB APRP (dB) 0
2
4 6 6 6 6
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
Bass control
UDA1335H
The bass control is available for the master channel of the UDA1335H. The bass range is from 0 to approximately 24 dB in steps of 2 dB. It should be noted that the negative bass values as defined in the "USB Device Class Definition for Audio Devices" are not supported by the UDA1335H; values below 0 dB are returned as 0 dB. The corner frequency is 75 Hz. Table 9 gives the mapping of the bBass value upon the actual bass setting of the USB APRP. Table 9 Bass control characteristics bBASS B7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 B5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 BASS USB HOST (dB) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 ... 5.25 ... 7.25 ... 9.25 ... 11.25 ... 13.25 ... 15.25 ... 17.25 ... 19.25 ... 21.25 ... 21.2 19.2 17.3 15.2 13.3 11.3 9.4 7.4 5.4 3.6 1.7 BASS USB APRP (dB) 0
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
bBASS B7 0 0 0 0 0 0 B6 1 1 1 1 1 1 B5 0 1 1 1 1 1 B4 1 0 0 1 1 1 B3 0 0 1 0 1 1 B2 1 1 1 1 1 1 B1 0 0 0 0 0 1 B0 1 1 1 1 1 1 BASS USB HOST (dB) 23.25 ... 25.25 ... 27.25 ... 29.25 ... 31.25 ... 31.75
UDA1335H
BASS USB APRP (dB) 23.2 23.2 23.2 23.2 23.2 23.2
Dynamic bass boost control Bass boost is one of the sound features as defined in the "USB Device Class Definition for Audio Devices". The bass boost control request data bBassBoost controls the position of the bass boost switch. The position can be either on or off. When bBassBoost is true the bass boost is activated. When bBassBoost is false the bass boost is off. When clipping prevention is active, the bass is reduced to avoid clipping with high volume settings. Bass boost is selectable via the configuration map. Clipping prevention When clipping prevention is ON and the sum of bass plus volume gives clipping, the bass is reduced. When clipping prevention is ON and the sum of treble plus volume gives clipping, the treble is reduced. Clipping prevention and clipping level are selectable via the configuration map. For more information about clipping prevention and the clipping level see the application documentation. De-emphasis De-emphasis is one of the properties which is not supported by the USB. De-emphasis for 44.1 kHz can be predefined in the configuration map selected at start-up of the UDA1335H.
Start-up and configuration of the UDA1335H START-UP OF THE UDA1335H After power-on, an internal power-on reset signal becomes HIGH after a certain RC time (R = 5000 , C = Cref). During 20 ms after power-on reset the UDA1335H has to initiate the internal settings. After the power-on reset the UDA1335H becomes master of the I2C-bus. The UDA1335H tries to read the eventually connected I2C-bus EEPROM and if an dedicated EEPROM is detected, the internal descriptors are overwritten and the selected port configuration is applied. If no EEPROM is detected, the UDA1335H tries to read the logic levels of GP3 and GP4. A choice can be made from four configuration maps via these two GP pins. CONFIGURATION SELECTION OF THE UDA1335H VIA A DIODE
MATRIX
The UDA1335H uses a configuration map to hold a number of specific configurable data on hardware, product, component and USB configuration level. At start-up, without EEPROM, the UDA1335H will scan the logic levels of GP3 and GP4. With these two GP pins it is possible to select one of the four possible configuration maps which are held in the external (E)PROM. This selection can be achieved via a diode matrix (see Fig.5).
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
After selecting an internal configuration map the user cannot change the chosen settings for the GP pins, internal configuration, descriptors etc. The UDA1335H supports a maximum of two push-buttons (six with I2C-bus expanders), which represent a certain feature of the UDA1335H. The UDA1335H supports a maximum of three outputs for e.g. user LEDs. For more information about the four configuration maps located in the (E)PROM and the input and output functions of the UDA1335H see the application documentation. CONFIGURATION OPTIONS OF THE UDA1335H VIA AN I2C-BUS EEPROM At start-up, the UDA1335H will address I2C-bus slave address 0 x A0H and will check the first two byte locations of the I2C-bus device with 0 x 55H and 0 x AAH. If a match occurs, the UDA1335H assumes that this I2C-bus device is an EEPROM which is dedicated to the UDA1335H. It will then read the configuration map stored in this EEPROM instead of one of four configuration maps located in the
UDA1335H
firmware of the microcontroller. The layout of the configuration map is fixed, the values (except bytes 0 and 1) are user definable. If the user wants to change e.g. the manufacturer name this can be achieved via the EEPROM code. The communication between the UDA1335H and the external I2C-bus device is based on the standard I2C-bus protocol given in the Philips specification "The I2C-bus and how to use it (including specifications)", which can be ordered using the code 9398 393 40011. The I2C-bus has two lines; a clock line SCL and a serial data line SDA (see Fig.6).
handbook, full pagewidth
3.3 V
3.3 V 22 k
3.3 V 22 k
3.3 V 22 k GP3 GP4
TR3 KEY 1 SW1 1.5 k 22 k KEY 2 SW2 1 1 D2 22 k TR1 TR2 22 k 1 2 3 4 6 10 nF 10 nF 22 pF 22 pF 22
MGL480
Vbus D1
2
22 k GP5
2
USB-B connector 5 Vbus
22
D- D+
Fig.5 Diode matrix selection.
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SDA t BUF t LOW tr tf t HD;STA t SP
Philips Semiconductors
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
Fig.6 Definition of timing of the I2C-bus.
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21
SCL t HD;STA P S t HD;DAT t HIGH t SU;DAT t SU;STA t SU;STO Sr
MBC611
P
Preliminary specification
UDA1335H
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
Table 10 Control options for the UDA1335H via the EEPROM configuration map; note 1 BYTE (HEX) 0 1 2 clocks control register AFFECTS COMMENTS recognition pattern do not change it recognition pattern do not change it selection ADC clock source divide factor 7 6 and 5 BIT 55H AAH
UDA1335H
VALUE
0 = ADC clock from APLL 1 = ADC clock from OSCAD 00 = ADC clock divided-by-1 01 = ADC clock divided-by-2 10 = ADC clock divided-by-4 11 = ADC clock divided-by-8
clock ADAC clock 48 MHz internal clock recovered PSIE/MMU ADC clock power on OSCAD 3 4 5 reset generator and APLL control register power control register analog modules ASR control register robust word clock serial I2S-bus output format
4 3 2 1 0
0 0 0 0 0 00H 00H
7 6 and 5
1 00 = I2S-bus 01 = 16-bit LSB 10 = 18-bit LSB 11 = 20-bit LSB
phase inversion (right output) bits per sample modi
4 3 and 2
0 = mono phase inversal off 1 = mono phase inversal on 00 = reserved 01 = 8-bit audio 10 = 16-bit audio 11 = 24-bit audio
mono or stereo operation ASR register start-up mode
1 0
0 = mono 1 = stereo 1
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
BYTE (HEX) 6 AFFECTS PGA control register input terminal 1 (all analog input topologies) reserved PGA internal setting (do not change it) PGA gain selection right channel COMMENTS BIT 7 6 5 to 3 X 0 000 = -3 dB 001 = 0 dB 010 = 3 dB 011 = 9 dB 100 = 15 dB 101 = 21 dB 110 = 27 dB 111 = 27 dB PGA gain selection left channel 2 to 0 000 = -3 dB 001 = 0 dB 010 = 3 dB 011 = 9 dB 100 = 15 dB 101 = 21 dB 110 = 27 dB 111 = 27 dB 7 PGA control register input terminal 2 (only for analog input topology 2) reserved PGA internal setting (do not change it) PGA gain selection right channel 7 6 5 to 3 X 0 000 = -3 dB 001 = 0 dB 010 = 3 dB 011 = 9 dB 100 = 15 dB 101 = 21 dB 110 = 27 dB 111 = 27 dB PGA gain selection left channel 2 to 0 000 = -3 dB 001 = 0 dB 010 = 3 dB 011 = 9 dB 100 = 15 dB 101 = 21 dB 110 = 27 dB 111 = 27 dB
UDA1335H
VALUE
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
BYTE (HEX) 8 AFFECTS ADIF control register reserved number of bits per audio sample to be transmitted to the host COMMENTS BIT 7 6 and 5 X
UDA1335H
VALUE
00 = reserved 01 = 8 bits audio samples 10 = 16 bits audio samples 11 = 24 bits audio samples
mono/stereo selection selection audio input channel selection high-pass filter of the decimation module I2S-bus input serial input format
4 3 2 1 and 0
0 = mono 1 = stereo 0 = digital serial audio input 1 = analog input 0 = high-pass filter off 1 = high-pass filter on 00 = I2S-bus 01 = 16-bit LSB 10 = 18-bit LSB 11 = 20-bit LSB
9
ADAC feature setting register
selection ADAC mode register audio feature mode de-emphasis channel manipulation synchronous/asynchronous mute control reset ADAC
7 6 and 5 4 3 2 1 0 7 6 and 5 4 3 and 2 1 and 0
0 11 0 = de-emphasis off 1 = de-emphasis on 0 = L L, R R 1 = L R, R L 0 1 0 1 00 1 00 00 = I2S-bus 01 = 16-bit LSB 10 = 18-bit LSB 11 = 20-bit LSB
A
ADAC lock mode register
selection ADAC mode register digital PLL lock speed digital PLL lock mode digital PLL mode serial I2S-bus input format
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
BYTE (HEX) B AFFECTS I/O selection register clipping expander selector output (GP2) mute/standby expander mute/standby USB APRP output pin 3 output pin 2 output pin 1 C D E F I2S-bus and topology selection register output pin function 1 output pin function 2 output pin function 3 output I2S-bus 4-pin or 6-pin I2S-bus 7 6 COMMENTS BIT 7 6 5 4 3 2 1 0
UDA1335H
VALUE 0 = clipping prevention OFF 1 = clipping prevention ON 0 = no I2C-bus expander used 1 = I2C-bus expander used 0 = selector state normal 1 = selector state inverted 0 = mute 1 = standby 0 = mute 1 = standby polarity output pins 0 = inverted logic 1 = normal logic functions are available if declared in ADC: 0 = mute LED; 1 = DBB LED 0 = no I2S-bus used 1 = I2S-bus used only if I2S-bus is used: 0 = 4-pin I2S-bus 1 = 6-pin I2S-bus 0 = HID not included 1 = HID included X low nibble: 1 = input topology 1 2 = input topology 2 3 = input topology 3 4 = input topology 4 all other values = input topology 1
HID usage reserved topology selection
5 4 3 2 1 0
10 11 12 13 14 15
rise time power amplifier, steps of 20 ms time between mute and play, steps of 1 s time between mute and standby, steps of 5 s selector preferred state (only applicable in input topology 2) DBB value steps of 1 dB with maximum 255 dB start-up volume value in dB 0 = terminal Input 1 or terminal input 2 0 = no DBB active 1 to FF = DBB active volume = -register value
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
BYTE (HEX) 16 17 18 19 1A/1B 1C/1D 1E/1F 20/21 22 23/24 25/26 27/28 29/2A : 23 + 2N/ 24 + 2N 30 45 1F0 210 212 25E 260 290 2D0 Notes string 0 string 1 string 2 string 3 sample frequency AFFECTS COMMENTS maximum distortion in dB LSB mid MSB pointer to device descriptor pointer to configuration descriptor pointer to HID descriptor pointer to HID report descriptor number of string pointers (N + 1) maximum for N is 31 pointer to string 0 pointer to string 1 pointer to string 2 pointer to string 3 : pointer to string N device descriptor configuration descriptor including ADC and HID descriptors wDescriptorLength HID report descriptor language string manufacturer string product string serial number(2) 32 025E 0260 0290 02D0 0030 0045 01F0 0210 BIT
UDA1335H
VALUE
1. An extensive description of the USB control options is available in the "USB Device Class Definition for Audio Devices". 2. The serial number is only supported in the external configuration map and not in the four internal configuration maps. The general purpose I/O pins (GP0 to GP5) and I2C-bus expander option The UDA1335H has 6 General Purpose (GP) I/O pins; these are pins GP0 to GP5. These can be used either for digital I/O functions or for general purposes. There are basically three port configurations: * No digital I/O communication * 4-pin digital I/O communication * 6-pin digital I/O communication. 1998 Aug 28 26
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
These port configurations can be chosen via the configuration map at start-up of the UDA1335H.
UDA1335H
The user can also make use of an I2C-bus expander. The usage of an I2C-bus expander (yes/no) can be indicated via the configuration map. Some of the supported HID functions are located in the I2C-bus expander. If this expander is not used, the HID functions normally located in the expander must be declared as "unassigned" in the HID report descriptor. The bit which indicates if an external expander is used must then be put on zero. Table 11 Definition of the general purpose pins and I2C-bus expander pins; notes 1 to 6 PINS NO I2S-BUS USAGE 4-PIN I2S-BUS USAGE 6-PIN I2S-BUS USAGE
General purpose I/O GP5 GP4 GP3 GP2 GP1 GP0 connect/disconnect HID input 2 HID input 1 selector output mute or standby output interrupt input connect/disconnect BCK output WS output DATA output DATA input interrupt input WS input BCK output WS output DATA output DATA input BCK input
I2C-bus expander; note 7 P0 P1 P2 P3 P4 P5 P6 P7 Notes 1. Connect/disconnect: This pin can be used to avoid malfunction during initialisation phase of the UDA1335H. While initialization takes place, the USB can be kept disconnected while the software of the microcontroller reads in the configuration map. When the UDA1335H is ready, the USB becomes connected and enumeration can start. Using the 6-pin I2S-bus, the connect/disconnect will be moved to the I2C-bus expander. 2. HID input 1 to 6 and interrupt input: A change on the expander can be signalled to the UDA1335H via the interrupt input. After detecting this signal the UDA1335H will decode the buttons. When no expander is used, the interrupt pin must be connected to the ground. The HID input pins and the interrupt input pin on the UDA1335H are scanned each 20 ms. If the interrupt in pin indicates a change on the expander, the expander input pins are scanned once. Using the 6-pin I2S-bus, the interrupt pin is not available and the inputs on the expander are scanned every 20 ms. All input pins must have a pull-up resistor. 3. Selector output: This pin can be used for switching the audio selector as illustrated in Fig.4. If the configuration map does not request this output pin, the output is always LOW. 4. Mute output: This output is activated if the isochronous signal is not available during a certain time. The output levels and the time are programmable in the configuration map. 5. Standby output: This output is activated if the UDA1335H is muted during a certain time. The output levels and the time are programmable in the configuration map. 6. Output pins 1 to 3: All the output pins are set via the I2C-bus. The function is according the configuration map. 7. For the I2C-bus expander, the PCF8574P remote 8-bit I/O expander for I2C-bus can be used. HID input 3 HID input 4 HID input 5 HID input 6 output pin 1 output pin 2 output pin 3 mute or standby output HID input 3 HID input 4 HID input 5 HID input 6 output pin 1 output pin 2 selector output mute or standby output connect/disconnect HID input 4 HID input 5 HID input 6 output pin 1 output pin 2 selector output mute or standby output
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
Filter characteristics
UDA1335H
The overall filter characteristic of the UDA1335H in flat mode is given in the Fig.7. The overall filter characteristic of the UDA1335H includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the FSDAC (fs = 44.1 kHz)
handbook, full pagewidth
-0
MGM110
-20 volume (dB) -40
-60
-80
-100
-120
-140
-160 0 10 20 30 40 50 60 70 80 f (kHz) 90 100
Fig.7 Overall filter characteristics of the UDA1335H.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
DSP extension port
UDA1335H
An external DSP can be used for adding extra sound processing features via the digital I/O-bus. The UDA1335H supports the standard I2S-bus data protocol and the LSB-justified serial data input format with word lengths of 16, 18 and 20 bits. Using the 4-pin digital I/O-bus the UDA1335H device acts as a master, controlling the BCK and WS signals. The period of the WS signal is determined by the number of samples in the 1 ms frame of the USB. This implies that the WS signal does not have a constant time period, but is jittery. Using the 6-pin digital I/O-pins GP2, GP3 and GP4 are output pins (master) and GP0, GP1 and GP5 are input pins (slave). The characteristic timing of the I2S-bus input interface is illustrated in Figs 8 and 9.
handbook, full pagewidth
LEFT
WS
RIGHT th;WS ts;WS
tr BCK
tBCK(H)
tf
tBCK(L)
Tcy
ts;DAT th;DAT
DATA
LSB
MSB
MGK003
Fig.8 Timing of digital I/O input signals.
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1998 Aug 28
WS 1 BCK DATA MSB B2 LSB MSB B2 2 LEFT 3 >=8 1 2 RIGHT 3 WS LEFT 16 BCK DATA MSB B2 B15 LSB 15 2 1
Philips Semiconductors
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
>=8
LSB MSB INPUT FORMAT I2S-BUS
RIGHT 16 15 2 1
MSB
B2
B15 LSB
LSB-JUSTIFIED FORMAT 16 BITS
30
WS
LEFT 18 17 16 15 2 1 18
RIGHT 17 16 15 2 1
BCK DATA MSB B2 B3 B4 B17 LSB MSB B2 B3 B4 B17 LSB
LSB-JUSTIFIED FORMAT 18 BITS
WS 20 BCK DATA MSB B2 19
LEFT 18 17 16 15 2 1 20 19 18
RIGHT 17 16 15 2 1
B3
B4
B5
B6
B19
LSB
MSB
B2
B3
B4
B5
B6
B19
LSB
MGK002
Preliminary specification
LSB-JUSTIFIED FORMAT 20 BITS
UDA1335H
Fig.9 Input formats.
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL All digital I/Os VI/O IO Tj Tstg Tamb Ves DC input/output voltage range output current VDDE = 5.0 V -0.5 - - - - - 25 - - PARAMETER CONDITIONS MIN. TYP.
UDA1335H
MAX.
UNIT
VDDE 4
V mA C C C
Temperature values junction temperature storage temperature operating ambient temperature 0 -55 0 -3000 -300 125 +150 70
Electrostatic handling electrostatic handling note 1 note 2 Notes 1. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 2. Equivalent to discharging a 200 pF capacitor through a 2.5 H series conductor. THERMAL CHARACTERISTICS SYMBOL Rthj-a PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 48 UNIT K/W +3000 +300 V V
RECOMMENDED OPERATING CONDITIONS SYMBOL VDDE VDD VI PARAMETER supply voltage periphery (I/O) supply voltage (core) DC input voltage range for D+ and D- for VINL and VINR for digital I/Os 0.0 - 0.0 - 0.5VDD - VDD - VDDE V V V 3.0 MIN. 4.75 5.0 3.3 TYP. MAX. 5.25 3.6 V V UNIT
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
DC CHARACTERISTICS VDDE = 5.0 V; VDD = 3.3 V; Tamb = 25 C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified. SYMBOL Supplies VDDE VDDI VDDA1 VDDA2 VDDA3 VDDO VDDX IDDE IDDI IDDA1 IDDA2 IDDA3 IDDO IDDX Ptot Pps digital supply voltage periphery digital supply voltage core analog supply voltage 1 analog supply voltage 2 analog supply voltage 3 operational amplifier supply voltage crystal oscillator supply voltage digital supply current periphery digital supply current core analog supply current 1 analog supply current 2 analog supply current 3 operational amplifier supply current crystal oscillator supply current total power dissipation total power dissipation in power saving mode note 4 note 1 4.75 3.0 3.0 3.0 3.0 3.0 3.0 - - - - - - - - - 5.0 3.3 3.3 3.3 3.3 3.3 3.3 3.7 39.0 3.6 8.0 0.9 3.0 1.2 200 1.2 PARAMETER CONDITIONS MIN. TYP.
UDA1335H
MAX.
UNIT
5.25 3.6 3.6 3.6 3.6 3.6 3.6 - - - - 9.0(2) - 13.0(3) - -
V V V V V V V mA mA mA mA mA mA mA mW mW
Inputs/outputs D+ and D- VI VO(H) VO(L) ILO VI(diff) VCM(diff) VSE(R)(th) CIN static DC input voltage static DC output voltage HIGH static DC output voltage LOW high impedance data line output leakage current differential input sensitivity differential common mode range single-ended receiver threshold voltage transceiver input capacitance pin to GND -0.5 RL = 15 k 2.8 connected to GND RL = 15 k connected to VDD - - 0.2 0.8 0.8 - - - - - - - - - VDDI 3.6 0.3 10 - 2.5 2.0 20 V V V A V V V pF
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
SYMBOL Digital input pins VIL VIH ILI CI PGA and ADC Vref(AD) Vref(ADC)(pos) Vref(ADC)(neg) VI(PGA) RI(PGA) reference voltage PGA and ADC positive reference voltage of the ADC negative reference voltage of the ADC DC input voltage VINL and VINR of the PGA DC input resistance at VINL and VINR of the PGA - - - - - 0.5VDDA2 VDDA2 0.0 0.5VDDA2 12.5 - - - - - LOW-level input voltage HIGH-level input voltage input leakage current input capacitance - - - - - - PARAMETER CONDITIONS MIN. TYP.
UDA1335H
MAX.
UNIT
0.3VDDE VDDE 1 5
V V A pF
0.7VDDE -
V V V V k
Filter stream DAC Vref(DA) VO(CM) RO(VOUT) RO(L) CO(L) Notes 1. This value depends strongly on the application. The specified value is the typical value obtained using the application diagram as illustrated in Fig.10. 2. At start-up of the OSCAD oscillator. 3. At start-up of the OSC48 oscillator. 4. Exclusive the IDDE current which depends on the components connected to the I/O pins. reference voltage DAC common mode output voltage output resistance at VOUTL and VOUTR output load resistance output load capacitance - - - 2.0 - 0.5VDDA1 0.5VDDA1 11 - - - - - - 50 V V k pF
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
AC CHARACTERISTICS VDDE = 5.0 V; VDDI = 3.3 V; Tamb = 25 C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - 12.00 1.0000 +0.0 +0.0 - - 0.0 0.0 - - TYP.
UDA1335H
MAX.
UNIT
Driver characteristics D+ and D- (full-speed mode) fo(s) tr tf trf(m) Vcr Ro(drive) fi(s) ffs(D) tfr(D) tJ1(diff) tJ2(diff) tW(EOP) tEOP(diff) tJR1 tJR2 tEOPR1 tEOPR2 audio sample output frequency rise time fall time rise/fall time matching (tr/tf) output signal crossover voltage driver output resistance steady-state drive CL = 50 pF CL = 50 pF 5 4 4 90 1.3 28 55 20 20 110 2.0 43 kHz ns ns % V
Data source timings D+ and D- (full-speed mode) audio sample input frequency full speed data rate frame interval source differential jitter to next transition source differential jitter for paired transitions source end of packet width differential to end of packet transition skew receiver data jitter tolerance to next transition receiver data jitter tolerance for paired transitions end of packet width at receiver must reject as end of packet end of packet width at receiver must accept as end of packet 5 11.97 0.9995 -3.5 -4.0 160 -2.0 -18.5 -9.0 40 82 55 12.03 1.0005 +3.5 +4.0 175 +5.0 +18.5 +9.0 - - kHz Mbits/s ms ns ns ns ns ns ns ns ns
Serial input/output data timing fs fi(WS) tr tf tBCK(H) tBCK(L) ts;DAT th;DAT ts;WS th;WS system clock frequency word selection input frequency rise time fall time bit clock HIGH time bit clock LOW time data set-up time data hold time word selection set-up time word selection hold time - 5 - - 55 55 10 20 20 10 12 - - - - - - - - - - 55 20 20 - - - - - - MHz kHz ns ns ns ns ns ns ns ns
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
SYMBOL PARAMETER CONDITIONS MIN. TYP.
UDA1335H
MAX.
UNIT
SDA and SCL lines (standard mode I2C-bus) fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tr tf CL(bus) fosc gm Ro Ci(XTAL1a) Ci(XTAL2a) Istart fosc gm Ro Ci(XTAL1b) Ci(XTAL2b) Istart SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition set-up time for STOP condition data hold time data set-up time rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line 0 4.7 4.0 4.7 4.0 4.7 4.0 5.0 250 - - - - - 12.8 0.6 4.5 4.1 3.7 - - - - - - - - - - - - 100 - - - - - - 0.9 - 1000 300 400 - - 30.2 2.3 5.2 5.0 13.0 kHz s s s s s s s ns ns ns pF
Oscillator 1 (system clock) oscillator frequency duty factor transconductance output resistance parasitic input capacitance XTAL1a parasitic input capacitance XTAL2a start-up current 48 50 22.1 1.1 4.8 4.6 7.6 - 50 13.6 2.0 5.4 4.6 5.0 MHz % mS k pF pF mA
Oscillator 2 (for ADC clock) oscillator frequency duty cycle transconductance output resistance parasitic input capacitance XTAL1b parasitic input capacitance XTAL2b start-up current 8.192 - 8.1 1.3 5.0 4.1 2.4 14.08 - 18.1 4.0 5.7 5.0 8.4 MHz % mA/V k pF pF mA
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
SYMBOL PARAMETER CONDITIONS MIN. TYP.
UDA1335H
MAX.
UNIT
Analog PLL (for ADC clock) fclk(PLL) tstrt(PO) tsu(PO) PGA and ADC Vi(FS)(rms) full-scale input voltage (RMS value) PGA gain = -3 dB PGA gain = 0 dB PGA gain = 3 dB PGA gain = 9 dB PGA gain = 15 dB PGA gain = 21 dB PGA gain = 27 dB Ci(PGA) (THD + N)/S input capacitance of the PGA total harmonic distortion plus noise-to-signal ratio fs = 44.1 kHz at input signal of 1 kHz; PGA gain = 0 dB; note 3 Vi (0 dB) (1.0 V RMS) - - Vi (-60 dB) S/N ct fs OL(FS) signal to noise ratio crosstalk between channels sample frequency (128fs) full-scale digital output level PGA gain = 0 dB; Vi = 1 V (RMS) Vi = 0.0 V PGA gain = 0 dB - - 90 - 0.640 - -85 0.0056 -30 3.2 95 100 - -2.0 -80 0.01 -20 10.0 - - 7.04 - dB % dB % dBA dB MHz dB - - - - - - - - 1414(5) 1000 708 355 178 89 44 - - - - - - - - 20 mV mV mV mV mV mV mV pF PLL clock frequency duty factor start-up time after power-on 8.1920 - - 5Cref(2) 11.2896 12.2880 50 - - - 10 - MHz % ms
Power-on reset power-on set-up-time note 1 ms
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
SYMBOL Filter stream DAC RES Vo(FS)(rms) SVRR Vo ct (THD + N)/S resolution full-scale output voltage (RMS value) VDD = 3.3 V 16 - - - - - 0.66 60 0.03 95 - - - - - PARAMETER CONDITIONS MIN. TYP.
UDA1335H
MAX.
UNIT
bits V dB dB dB
supply voltage ripple rejection at fripple = 1 kHz; VDDA and VDDO Vripple(p-p) = 0.1 V channel unbalance crosstalk between channels total harmonic distortion plus noise-to-signal ratio maximum volume RL = 5 k fs = 44.1 kHz; RL = 5 k; note 4 at input signal of 1 kHz (0 dB) at input signal of 1 kHz (-60 dB)
- - - - 90
-90 0.0032 -30 3.2 95
-80 0.01 -20 10 -
dB % dB % dB
S/N Notes
signal-to-noise ratio at bipolar zero
A-weighting at code 0000H
1. Strongly depends on the external decoupling capacitor connected to Vref(DA). 2. Cref in F. 3. Measured with the APLL as ADC clock source. 4. Measured with I2S-bus input as digital source. 5. Although a level of 1.414 V (RMS) would be required to optimal drive the ADC in this gain setting, this level can not be used. Due to the 3.3 V supply voltage input, signals of 1.17 V (RMS) and higher will result in clipping. APPLICATION INFORMATION The UDA1335H can only be used in combination with an external (E)PROM. This (E)PROM can be connected to the port pins (P0 and P2) of the UDA1335H and must contain the firmware for the microcontroller. The UDA1335H will be delivered with standard USB compliant firmware. The I2C-bus EEPROM is optional and can be used to configure client specific configurations and descriptors. More information about the firmware, descriptors and configurations can be obtained from several application notes.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
UDA1335H
handbook, full pagewidth
C34 47 F (16 V) C38 100 nF (63 V) VSSA1 39
+VA R35 1 C32 47 F (16 V) C21 100 nF (63 V) VDDA1 VSSA2 38 44
+VA R27 1
VDDA2 42
BCKI digital input playback WSI DI
GP0/BCKI GP5/WSI GP1/DI
17 15 13
BCK digital input recording WS DA
BCK WS DA
61 59 57
+VC X4
1 2 3 4
L1
1 2 3 4 8 7 6 5
VUSB
R48 1.5 k R7 22 R16 D+ 22 D- 6
8
UDA1335H
C15 10 nF (50 V)
C16 10 nF (50 V)
C18 22 pF (63 V)
C17 22 pF (63 V)
C8 analog input recording 47 F (16 V) C22 47 F (16 V) C44 10 nF (63 V) L5 1.5 H
VINR
47
VINL
43
1
XTAL2b
26
C38 12 pF (63 V) X1 C37 4.7 pF (50 V) XTAL2a ADC XTAL C5 18 pF (50 V) L8 BLM32A07 L7 BLM32A07 L6 BLM32A07 C47 100 F (16 V) C46 100 F (16 V) C6 18 pF (50 V) 10 VSSI C25 100 nF (63 V) C24 100 nF (63 V)
MBK839
48 MHz XTAL1b
25
XTAL1a
53 54
VA(ext)
+VA +VC +VD C45 100 F (16 V)
9 VDDI
11 VSSE C26 100 nF (63 V) C27 100 nF (63 V)
12 VDDE
VD(ext)
L2 BLM32A07
L3 BLM32A07
GND
R17 1 +VC
R25 1 +VD
Fig.10 Application diagram (continued in Fig.11).
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
UDA1335H
+V handbook, full pagewidthA C7 47 F (16 V) C19 100 nF (63 V) VSSA3 55 R10 1 C11 100 nF (63 V)
+VA R8 1
VDDA3 VRN 52 49
VRP 51 56 58 60 62 64 3 5 7 50 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ALE D7 D6 D5 D4 D3 D2 D1 D0 LE OE 18 17 14 13 8 7 4 3 11 1 10 14 16 18 20 22 23 31 48 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 PSEN EA +VD R20 1 C36 100 nF (63 V) A0 A1 A2 VSS 21 19 40 41 SDA SCL Vref(DA) Vref(AD) C28 100 nF (63 V) C35 47 F (16 V) analog output playback C31 47 F (16 V) C29 100 nF (63 V) C41 47 F (16 V) 2 1 2 3 4 R28 4.7 k 8 VDD PTC SCL SDA R38 10 k R39 10 k 1 (I2C-bus) +VD +VD 19 16 15 12 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC C24 GND +VD 100 nF (50 V) A0 A1 A2 A3 A4 A5 A6 A7 A8 10 9 8 7 6 5 4 3 25 11 12 13 15 16 17 18 19 O0 O1 O2 O3 O4 O5 O6 O7
D1 74HCT373D
9 6 5 2 20
D2 A9 24 EEPM27128
A10 A11 A12 A13 OE CE PGM VPP 21 23 2 26 22 20 27 1 14 28 VCC C25 GND +VD 100 nF (50 V)
UDA1335H
D4 PCF85116-3
7 6 5
37
VOUTR
34
VOUTL
C48 47 F (16 V)
2 1 63
GP4/BCKO GP3/WSO GP2/DO
BCKO WSO DO
digital output playback
36 35 4 33 VSSO C33 100 nF (63 V) C39 47 F (16 V) R43 1 +VA 32 VDDO 24 VSSX C28 100 nF (63 V) C18 100 nF (63 V) 28
RTCB TC SHTCB
VDDX
L13 BLM32A07
R26 1 +VC
MBK840
Fig.11 Application diagram (continued from Fig.10).
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
UDA1335H
SOT319-2
c
y X
51 52
33 32 ZE
A
e E HE A A2 A1 (A 3) Lp bp 64 1 wM D HD ZD B vM B 19 vMA 20 detail X L
pin 1 index
wM
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm.
UDA1335H
If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
UDA1335H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Aug 28
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP)
NOTES
UDA1335H
1998 Aug 28
43
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545102/750/01/pp44
Date of release: 1998 Aug 28
Document order number:
9397 750 03922

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